Gated clock. Clock net cpu0/rst_long is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net main_mem_B/_n0050 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net main_mem_B/_n0049 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. The signal <sw<0>_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <sw<1>_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <sw<2>_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <btn<0>_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <btn<1>_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <btn<2>_IBUF> is incomplete. The signal does not drive any load pins in the design. To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp takt0/DCM_inst/takt0/DCM_inst, consult the device Interactive Data Sheet.