Logical network clk_aux has no load. The above warning message base_net_load_rule is repeated 6 more times for the following (max. 5 shown): btn<2>_IBUF, btn<1>_IBUF, btn<0>_IBUF, sw<2>_IBUF, sw<1>_IBUF To see the details of these warning messages, please use the -detail switch. No environment variables are currently set. The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "sram0/bufg_clk" (output signal=clk_cpu), BUFG symbol "takt0/bufg_1" (output signal=clk_sram), BUFG symbol "takt0/bufg_3" (output signal=takt0/clk1) All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. Gated clock. Clock net cpu0/rst_long is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net main_mem_B/_n0050 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net main_mem_B/_n0049 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. The signal <sw<0>_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <sw<1>_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <sw<2>_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <btn<0>_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <btn<1>_IBUF> is incomplete. The signal does not drive any load pins in the design. The signal <btn<2>_IBUF> is incomplete. The signal does not drive any load pins in the design. To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp takt0/DCM_inst/takt0/DCM_inst, consult the device Interactive Data Sheet.