The signal sw<0>_IBUF has no load. PAR will not attempt to route this signal. The signal sw<1>_IBUF has no load. PAR will not attempt to route this signal. The signal sw<2>_IBUF has no load. PAR will not attempt to route this signal. The signal btn<0>_IBUF has no load. PAR will not attempt to route this signal. The signal btn<1>_IBUF has no load. PAR will not attempt to route this signal. The signal btn<2>_IBUF has no load. PAR will not attempt to route this signal. CLK Net:rst_cpu may have excessive skew because CLK Net:cpu0/rst_long may have excessive skew because CLK Net:main_mem_B/_n0050 may have excessive skew because CLK Net:main_mem_B/_n0049 may have excessive skew because CLK Net:clk_IBUFG may have excessive skew because Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. Review the timing report using Timing Analyzer (In ISE select "Post-Place & Route Static Timing Report"). Go to the failing constraint(s) and select the "Timing Improvement Wizard" link for suggestions to correct each problem. N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. There are 6 sourceless or loadless signals in this design. This design will not pass the DRC check run by Bitgen.