"main.v" line 159 Connection to input port 'type' does not match port size "microstore.v" line 51 Connection to output port 'DOP' does not match port size "microstore.v" line 54 Connection to input port 'DI' does not match port size "microstore.v" line 55 Connection to input port 'DIP' does not match port size "microstore.v" line 94 Connection to output port 'DOP' does not match port size "microstore.v" line 97 Connection to input port 'DI' does not match port size "microstore.v" line 98 Connection to input port 'DIP' does not match port size "gldata.v" line 248 Connection to input port 'DIB' does not match port size "main.v" line 604: Parameter 2 is not constant in call of system task $display. "main.v" line 664: The signals <dataout_B> are missing in the sensitivity list of always block. "cpu20a.v" line 760: Parameter 2 is not constant in call of system task $display. "cpu20a.v" line 765: Parameter 2 is not constant in call of system task $display. "cpu20a.v" line 774: Parameter 2 is not constant in call of system task $display. "sramcontrol.v" line 310: The signals <addr_sr_A> are missing in the sensitivity list of always block. Input <address<9>> is never used. Input <read_en> is never used. Signal <gl_dopa0> is assigned but never used. Signal <gl_dipa> is used but never assigned. Tied to value 0. Signal <gl_dia0> is used but never assigned. Tied to value 0. Input <address<9>> is never used. Input <read_en> is never used. Signal <gl_dopa0> is assigned but never used. Signal <gl_dipa> is used but never assigned. Tied to value 0. Signal <gl_dia0> is used but never assigned. Tied to value 0. Output <carry> is never assigned. Tied to value 0. Output <overflow> is never assigned. Tied to value 0. Input <amem<1:0>> is never used. Signal <RxD_data_error> is assigned but never used. Input <dia<31:10>> is never used. Input <ena<3:2>> is never used. Input <enb<3:2>> is never used. Input <wea<3:2>> is never used. Input <addra<1:0>> is never used. Input <addrb<1:0>> is never used. Input <ssra> is never used. Signal <gl_dopa0> is assigned but never used. Signal <gl_dopa1> is assigned but never used. Signal <gl_dopa2> is assigned but never used. Signal <gl_dopa3> is assigned but never used. Signal <gl_dopb0> is assigned but never used. Signal <gl_dopb1> is assigned but never used. Signal <gl_dopb2> is assigned but never used. Signal <gl_dopb3> is assigned but never used. Signal <ssra0> is used but never assigned. Tied to value 0. Signal <ssra1> is used but never assigned. Tied to value 0. Signal <ssra2> is used but never assigned. Tied to value 0. Signal <ssra3> is used but never assigned. Tied to value 0. Signal <gl_dipa> is used but never assigned. Tied to value 0. Signal <gl_dipb> is used but never assigned. Tied to value 0. Signal <gl_ssrb> is used but never assigned. Tied to value 0. Signal <gl_dib> is used but never assigned. Tied to value 00000000. Signal <web> is never used or assigned. Found 8-bit latch for signal <doa_0>. HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefuly review if it was in your intentions to describe such a latch. Found 8-bit latch for signal <dob_0>. HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefuly review if it was in your intentions to describe such a latch. Input <addr<31:13>> is never used. Input <addr<1:0>> is never used. Input <rst> is never used. Signal <gl_dopa0> is assigned but never used. Signal <gl_dopa1> is assigned but never used. Signal <gl_dopa2> is assigned but never used. Signal <gl_dopa3> is assigned but never used. Signal <gl_dipa> is used but never assigned. Tied to value 0. Signal <gl_doa> is never used or assigned. Signal <next_micr_pc> is assigned but never used. Signal <carry> is assigned but never used. Signal <datao> is never used or assigned. Signal <mic_inst<5:4>> is assigned but never used. Signal <overflow> is assigned but never used. Signal <mic_inst_h<31:16>> is assigned but never used. Signal <irRead> is never used or assigned. Signal <opA> is assigned but never used. Signal <dummy> is assigned but never used. Signal <zero> is assigned but never used. Found 32-bit latch for signal <tosout>. Found 32-bit latch for signal <debugout>. Signal <CLKFX180> is assigned but never used. Signal <CLK2X180> is assigned but never used. Signal <STATUS> is assigned but never used. Signal <CLK180> is assigned but never used. Signal <CLK90> is assigned but never used. Signal <CLK2X> is assigned but never used. Signal <CLK270> is assigned but never used. Signal <PSEN> is used but never assigned. Tied to value 0. Signal <PSDONE> is assigned but never used. Signal <PSCLK> is used but never assigned. Tied to value 0. Signal <PSINCDEC> is used but never assigned. Tied to value 0. Signal <btnout> is never used or assigned. Input <datin<23:18>> is never used. Input <datin<15:0>> is never used. Signal <cg_clkb> is assigned but never used. Signal <datinreg> is never used or assigned. Signal <cg_addra> is never used or assigned. Signal <cg_addrb> is assigned but never used. Signal <loadpix> is never used or assigned. Signal <gl_dia> is never used or assigned. Signal <gl_dib> is never used or assigned. Signal <right> is assigned but never used. Signal <cg_dia> is never used or assigned. Signal <cg_dib> is never used or assigned. Signal <gl_doa> is never used or assigned. Signal <gl_dob<7>> is assigned but never used. Signal <new_dob<7:5>> is assigned but never used. Signal <cg_doa> is never used or assigned. Signal <cg_dob> is never used or assigned. Signal <cg_enb> is assigned but never used. Signal <upper> is assigned but never used. Signal <gl_dobx<7>> is assigned but never used. Signal <gl_clka> is assigned but never used. Signal <gl_clkb> is assigned but never used. Signal <cg_clka> is assigned but never used. Input <btn<1:0>> is never used. Input <clk_aux> is never used. Input <sw<2:0>> is never used. Signal <ssrmem_w> is assigned but never used. Signal <btnl<2>> is assigned but never used. Signal <btnl<1:0>> is never used or assigned. Signal <rdack_B> is used but never assigned. Tied to value 0. Signal <wrtack_A> is used but never assigned. Tied to value 0. Signal <wrtack_B> is used but never assigned. Tied to value 0. Signal <addr_mem_b_vga<31:15>> is assigned but never used. Signal <rdack> is assigned but never used. Signal <wrtack> is assigned but never used. Signal <rxd_eofp> is assigned but never used. Signal <btnc0> is used but never assigned. Tied to value 0. Signal <btnc1> is used but never assigned. Tied to value 0. Signal <clk_cpu_na> is assigned but never used. Signal <clk1> is assigned but never used. Signal <rxd_idle> is assigned but never used. Signal <sel_regs> is never used or assigned. Signal <mwire> is assigned but never used. Signal <locked> is assigned but never used. Signal <btnu0> is never used or assigned. Signal <btnu1> is never used or assigned. Signal <btnu2> is assigned but never used. Signal <irq_cpu> is never used or assigned. Signal <debugout<31:8>> is assigned but never used. Signal <datamem_D<23:20>> is assigned but never used. Signal <datamem_D<15:8>> is assigned but never used. Signal <rack_vga> is assigned but never used. Signal <byte_type> is never used or assigned. Signal <switch_A_C> is assigned but never used. Signal <rst_sec> is never used or assigned. Signal <ssrmem> is assigned but never used. Signal <btnc> is assigned but never used. Found 4-bit latch for signal <sel_C_reg>. Found 4-bit latch for signal <sel_A_reg>. HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. HDL ADVISOR - A 2-bit shift register was found for signal <RxD_sync_inv<1>> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. HDL ADVISOR - A 2-bit shift register was found for signal <rst_cpu> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. HDL ADVISOR - A 2-bit shift register was found for signal <rst_sram> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. FF/Latch <pixshift_0> (without init value) has a constant value of 0 in block <vgacontrol>. Due to other FF/Latch trimming, FF/Latch <pixshift_1> (without init value) has a constant value of 0 in block <vgacontrol>. Due to other FF/Latch trimming, FF/Latch <pixshift_2> (without init value) has a constant value of 0 in block <vgacontrol>. FF/Latch <enbus_1> is unconnected in block <memadap_read_b>. FF/Latch <bstateold> is unconnected in block <debounce2>. FF/Latch <ir_30> is unconnected in block <cpu0>. FF/Latch <ir_31> is unconnected in block <cpu0>. FF/Latch <enbus_1> is unconnected in block <mar0_A>. FF/Latch <RxD_endofpacket> is unconnected in block <asr0>. HDL ADVISOR - A 2-bit shift register was found for signal <RxD_sync_inv<1>> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. HDL ADVISOR - A 2-bit shift register was found for signal <rst_cpu> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. HDL ADVISOR - A 2-bit shift register was found for signal <rst_sram> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. The FF/Latch <sel_A_reg_1> in Unit <main> is equivalent to the following FF/Latch, which will be removed : <sel_C_reg_1> The FF/Latch <sel_C_reg_3> in Unit <main> is equivalent to the following 2 FFs/Latches, which will be removed : <sel_C_reg_2> <sel_C_reg_0> The FF/Latch <sel_A_reg_3> in Unit <main> is equivalent to the following 2 FFs/Latches, which will be removed : <sel_A_reg_2> <sel_A_reg_0> The FF/Latch <31> in Unit <LPM_LATCH_5> is equivalent to the following 15 FFs/Latches, which will be removed : <30> <29> <28> <27> <26> <25> <24> <23> <22> <21> <20> <19> <18> <17> <16> FF/Latch <micr_pc_9> (without init value) has a constant value of 0 in block <cpu>. FF/Latch <31> (without init value) has a constant value of 0 in block <LPM_LATCH_5>. FF/Latch <sel_A_reg_1> (without init value) has a constant value of 0 in block <main>. FF/Latch <debounce2/bstate> is unconnected in block <main>. FF/Latch <debounce2/bstateold> is unconnected in block <main>. FF/Latch <gl_addr_akt_13> is unconnected in block <vgacontrol>. FF/Latch <gl_addr_reset_13> is unconnected in block <vgacontrol>. FF/Latch <irq_aux_1> has a constant value of 0 in block <main>. FF/Latch <irq_aux_2> has a constant value of 0 in block <main>. Unit <mem_adaptor_be_w>: instances <Mshift__n0007>, <Mshift__n0010> of unit <LPM_CLSHIFT_3> are equivalent, second instance is removed Unit main: 148 internal tristates are replaced by logic (pull-up yes): Unit cpu: 96 internal tristates are replaced by logic (pull-up yes): FF/Latch <memadap_read_b/type_o_0> has a constant value of 0 in block <main>. Due to other FF/Latch trimming, FF/Latch <memadap_read_b/type_o_1> has a constant value of 0 in block <main>. FF/Latch <asr0/RxD_endofpacket> is unconnected in block <main>. FF/Latch <asr0/gap_count_0> is unconnected in block <main>. FF/Latch <asr0/gap_count_1> is unconnected in block <main>. FF/Latch <asr0/gap_count_2> is unconnected in block <main>. FF/Latch <asr0/gap_count_3> is unconnected in block <main>. FF/Latch <asr0/gap_count_4> is unconnected in block <main>. FF/Latch <cpu0/ir_30> is unconnected in block <main>. FF/Latch <cpu0/ir_31> is unconnected in block <main>. FF/Latch <cpu0/debugout_15> is unconnected in block <main>. FF/Latch <cpu0/debugout_14> is unconnected in block <main>. FF/Latch <cpu0/debugout_13> is unconnected in block <main>. FF/Latch <cpu0/debugout_12> is unconnected in block <main>. FF/Latch <cpu0/debugout_11> is unconnected in block <main>. FF/Latch <cpu0/debugout_10> is unconnected in block <main>. FF/Latch <cpu0/debugout_9> is unconnected in block <main>. FF/Latch <cpu0/debugout_8> is unconnected in block <main>. FF/Latch <cpu0/tosout_31> is unconnected in block <main>. FF/Latch <cpu0/tosout_30> is unconnected in block <main>. FF/Latch <cpu0/tosout_29> is unconnected in block <main>. FF/Latch <cpu0/tosout_28> is unconnected in block <main>. FF/Latch <cpu0/tosout_27> is unconnected in block <main>. FF/Latch <cpu0/tosout_26> is unconnected in block <main>. FF/Latch <cpu0/tosout_25> is unconnected in block <main>. FF/Latch <cpu0/tosout_24> is unconnected in block <main>. FF/Latch <cpu0/tosout_23> is unconnected in block <main>. FF/Latch <cpu0/tosout_22> is unconnected in block <main>. FF/Latch <cpu0/tosout_21> is unconnected in block <main>. FF/Latch <cpu0/tosout_20> is unconnected in block <main>. FF/Latch <cpu0/tosout_19> is unconnected in block <main>. FF/Latch <cpu0/tosout_18> is unconnected in block <main>. FF/Latch <cpu0/tosout_17> is unconnected in block <main>. FF/Latch <cpu0/tosout_16> is unconnected in block <main>. FF/Latch <cpu0/tosout_15> is unconnected in block <main>. FF/Latch <cpu0/tosout_14> is unconnected in block <main>. FF/Latch <cpu0/tosout_13> is unconnected in block <main>. FF/Latch <cpu0/tosout_12> is unconnected in block <main>. FF/Latch <cpu0/tosout_11> is unconnected in block <main>. FF/Latch <cpu0/tosout_10> is unconnected in block <main>. FF/Latch <cpu0/tosout_9> is unconnected in block <main>. FF/Latch <cpu0/tosout_8> is unconnected in block <main>. FF/Latch <cpu0/tosout_7> is unconnected in block <main>. FF/Latch <cpu0/tosout_6> is unconnected in block <main>. FF/Latch <cpu0/tosout_5> is unconnected in block <main>. FF/Latch <cpu0/tosout_4> is unconnected in block <main>. FF/Latch <cpu0/tosout_3> is unconnected in block <main>. FF/Latch <cpu0/tosout_2> is unconnected in block <main>. FF/Latch <cpu0/tosout_1> is unconnected in block <main>. FF/Latch <cpu0/tosout_0> is unconnected in block <main>. FF/Latch <main_mem_B/dob_0_7> is unconnected in block <main>. FF/Latch <mar0_A/enbus_1> is unconnected in block <main>. FF/Latch <memadap_read_b/enbus_1> is unconnected in block <main>. FF/Latch <memadap_read_b/arest_0> is unconnected in block <main>. FF/Latch <memadap_read_b/arest_1> is unconnected in block <main>. HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.