#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "rxd" LOC = "T13" ; NET "txd" LOC = "R13" ; NET "anod[0]" LOC = "D14" ; NET "anod[1]" LOC = "G14" ; NET "anod[2]" LOC = "F14" ; NET "anod[3]" LOC = "E13" ; NET "b" LOC = "R11"; NET "btn[0]" LOC = "M13" ; NET "btn[1]" LOC = "M14" ; NET "btn[2]" LOC = "L13" ; NET "clk" LOC = "T9"; NET "g" LOC = "T12"; NET "hs" LOC = "R9"; NET "ld[0]" LOC = "K12" ; NET "ld[1]" LOC = "P14" ; NET "ld[2]" LOC = "L12" ; NET "ld[3]" LOC = "N14" ; NET "ld[4]" LOC = "P13" ; NET "ld[5]" LOC = "N12" ; NET "ld[6]" LOC = "P12" ; NET "ld[7]" LOC = "P11" ; NET "ps2c" LOC = "M16"; NET "ps2d" LOC = "M15"; NET "r" LOC = "R12"; NET "rst" LOC = "L14"; NET "sevseg[7]" LOC = "E14" ; NET "sevseg[6]" LOC = "G13" ; NET "sevseg[5]" LOC = "N15" ; NET "sevseg[4]" LOC = "P15" ; NET "sevseg[3]" LOC = "R16" ; NET "sevseg[2]" LOC = "F13" ; NET "sevseg[1]" LOC = "N16" ; NET "sevseg[0]" LOC = "P16" ; NET "sw[0]" LOC = "F12" ; NET "sw[1]" LOC = "G12" ; NET "sw[2]" LOC = "H14" ; NET "sw[3]" LOC = "H13" ; NET "sw[4]" LOC = "J14" ; NET "sw[5]" LOC = "J13" ; NET "sw[6]" LOC = "K14" ; NET "sw[7]" LOC = "K13" ; NET "vs" LOC = "T10"; NET "addr_sr<0>" LOC = "L5"; NET "addr_sr<10>" LOC = "G5"; NET "addr_sr<11>" LOC = "H3"; NET "addr_sr<12>" LOC = "H4"; NET "addr_sr<13>" LOC = "J4"; NET "addr_sr<14>" LOC = "J3"; NET "addr_sr<15>" LOC = "K3"; NET "addr_sr<16>" LOC = "K5"; NET "addr_sr<17>" LOC = "L3"; NET "addr_sr<1>" LOC = "N3"; NET "addr_sr<2>" LOC = "M4"; NET "addr_sr<3>" LOC = "M3"; NET "addr_sr<4>" LOC = "L4"; NET "addr_sr<5>" LOC = "G4"; NET "addr_sr<6>" LOC = "F3"; NET "addr_sr<7>" LOC = "F4"; NET "addr_sr<8>" LOC = "E3"; NET "addr_sr<9>" LOC = "E4"; NET "ce_0_sr" LOC = "P7"; NET "ce_1_sr" LOC = "N5"; NET "data_io_0_sr<0>" LOC = "N7"; NET "data_io_0_sr<10>" LOC = "F2"; NET "data_io_0_sr<11>" LOC = "H1"; NET "data_io_0_sr<12>" LOC = "J2"; NET "data_io_0_sr<13>" LOC = "L2"; NET "data_io_0_sr<14>" LOC = "P1"; NET "data_io_0_sr<15>" LOC = "R1"; NET "data_io_0_sr<1>" LOC = "T8"; NET "data_io_0_sr<2>" LOC = "R6"; NET "data_io_0_sr<3>" LOC = "T5"; NET "data_io_0_sr<4>" LOC = "R5"; NET "data_io_0_sr<5>" LOC = "C2"; NET "data_io_0_sr<6>" LOC = "C1"; NET "data_io_0_sr<7>" LOC = "B1"; NET "data_io_0_sr<8>" LOC = "D3"; NET "data_io_0_sr<9>" LOC = "P8"; NET "data_io_1_sr<0>" LOC = "P2"; NET "data_io_1_sr<10>" LOC = "G1"; NET "data_io_1_sr<11>" LOC = "F5"; NET "data_io_1_sr<12>" LOC = "C3"; NET "data_io_1_sr<13>" LOC = "K2"; NET "data_io_1_sr<14>" LOC = "M1"; NET "data_io_1_sr<15>" LOC = "N1"; NET "data_io_1_sr<1>" LOC = "N2"; NET "data_io_1_sr<2>" LOC = "M2"; NET "data_io_1_sr<3>" LOC = "K1"; NET "data_io_1_sr<4>" LOC = "J1"; NET "data_io_1_sr<5>" LOC = "G2"; NET "data_io_1_sr<6>" LOC = "E1"; NET "data_io_1_sr<7>" LOC = "D1"; NET "data_io_1_sr<8>" LOC = "D2"; NET "data_io_1_sr<9>" LOC = "E2"; NET "lb_0_sr" LOC = "P6"; NET "lb_1_sr" LOC = "P5"; NET "oe_sr" LOC = "K4"; NET "ub_0_sr" LOC = "T4"; NET "ub_1_sr" LOC = "R4"; NET "we_sr" LOC = "G3"; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50 %; #NET "clk_cpu" TNM = "clk_cpu" #TIMESPEC "TS_clk_cpu" = PERIOD "clk_cpu" 30ns HIGH 50 % #INST "vgacontrol0/chargen_ram" #INIT_00 = 812424243C241881001824242424188100000000000000000000000000000000 # #INST "vgacontrol0/chargen_ram" #INIT_01 = 0000000000000000000000000000000000000000000000000000000000000000 # # #INST "vgacontrol0/chargen_ram" #INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000 # #INST "vgacontrol0/chargen_ram" #INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000 # #INST "vgacontrol0/chargen_ram" #INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000 # #INST "vgacontrol0/chargen_ram" #INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000 # #INST "vgacontrol0/chargen_ram" #INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000 # #INST "vgacontrol0/chargen_ram" #INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000 # #INST "vgacontrol0/chargen_ram" #INIT_08 = 0014147F147F1414000000000000141400080008080808080000000000000000 # #INST "vgacontrol0/chargen_ram" #INIT_09 = 0000000000000808003A444628102818000026160834320000083C0A1C281E08 # #INST "vgacontrol0/chargen_ram" #INIT_0A = 000808087F0808080008492A1C2A490800100804040408100004081010100804 # #INST "vgacontrol0/chargen_ram" #INIT_0B = 0040201008040201000C0C0000000000000000007F00000008040C0C00000000 # #INST "vgacontrol0/chargen_ram" #INIT_0C = 001C22020C02221C003E10080402221C001C080808081808001C22222A22221C # #INST "vgacontrol0/chargen_ram" #INIT_0D = 001010100804023E001C22223C20221C001C22023C20203E000E04043E24140C # #INST "vgacontrol0/chargen_ram" #INIT_0E = 08040C0C000C0C0000000C0C000C0C00001C22021E22221C001C22221C22221C # #INST "vgacontrol0/chargen_ram" #INIT_0F = 000800080402221C00201008040810200000007F007F00000004081020100804 # #INST "vgacontrol0/chargen_ram" #INIT_10 = 001C22202020221C003C22223C22223C002222223E22221C001C202E2A2E221C # #INST "vgacontrol0/chargen_ram" #INIT_11 = 001C22222E20221C002020203E20203E003E20203C20203E003C22222222223C # #INST "vgacontrol0/chargen_ram" #INIT_12 = 0022222438242222001824240404040E001C08080808081C002222223E222222 # #INST "vgacontrol0/chargen_ram" #INIT_13 = 001C22222222221C002222262A2A32220041414149556341001E101010101010 # #INST "vgacontrol0/chargen_ram" #INIT_14 = 001C22021C20221C002224283C22223C061C22222222221C001010101C12121C # #INST "vgacontrol0/chargen_ram" #INIT_15 = 0014142A2A4141410008081414222222001C222222222222000808080808083E # #INST "vgacontrol0/chargen_ram" #INIT_16 = 001C10101010101C003E20100804023E00080808081422220022221408142222 # #INST "vgacontrol0/chargen_ram" #INIT_17 = 7F000000000000000000000000221408001C04040404041C0001020408102040 # #INST "vgacontrol0/chargen_ram" #INIT_18 = 001C2020201C0000002C1212121C1010001D22221E021C000000000000000810 # #INST "vgacontrol0/chargen_ram" #INIT_19 = 1C021E22221D0000001010103810120C001C203E221C0000000D1212120E0202 # #INST "vgacontrol0/chargen_ram" #INIT_1A = 00242830282420203008080808000800000808080800080000222222322C2020 # #INST "vgacontrol0/chargen_ram" #INIT_1B = 001C2222221C000000121212122C00000049494949B600000008080808080818 # ## ^^^^ Korrektur am m, war 41 # #INST "vgacontrol0/chargen_ram" #INIT_1C = 00380418201C000000202020302C000004041C24241A000010101C12122C0000 # #INST "vgacontrol0/chargen_ram" #INIT_1D = 00225549414100000008142222220000001A24242424000000080808081C0800 # #INST "vgacontrol0/chargen_ram" #INIT_1E = 000C10102010100C003C1008043C00001C020E12121200000022140814220000 # #INST "vgacontrol0/chargen_ram" #INIT_1F = 0000000000000000000000064930000000300808040808300008080808080808 INST "main_mem_B/gldata_ram0" INIT_00 = 0303030303030303030303030303030303030303030303030303030303034440; INST "main_mem_B/gldata_ram0" INIT_01 = 0303030303030303030303030303030303030303030303030303030303030303; INST "main_mem_B/gldata_ram0" INIT_02 = 0303030303030303030303030303030303030303030303030303030303030303; INST "main_mem_B/gldata_ram0" INIT_03 = 0000000000000000000000000000000000000000000000020202020003020202; INST "main_mem_B/gldata_ram0" INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000; INST "main_mem_B/gldata_ram0" INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000; INST "main_mem_B/gldata_ram1" INIT_00 = 3F3E3D3C3B3A393837363534333231302F2E2D2C2B2A29282726252423224541; INST "main_mem_B/gldata_ram1" INIT_01 = 5F5E5D5C5B5A595857565554535251504F4E4D4C4B4A49484746454443424140; INST "main_mem_B/gldata_ram1" INIT_02 = 7F7E7D7C7B7A797877767574737271706F6E6D6C6B6A69686766656463626160; INST "main_mem_B/gldata_ram1" INIT_03 = 0000000000000000000000000000000000000000000000020202020003020202; INST "main_mem_B/gldata_ram1" INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000; INST "main_mem_B/gldata_ram1" INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000; INST "main_mem_B/gldata_ram2" INIT_00 = 0202030303030303030303030303030303030303030303030303030303034642; INST "main_mem_B/gldata_ram2" INIT_01 = 0303030303030303030303030303030303030303030303030303030303030303; INST "main_mem_B/gldata_ram2" INIT_02 = 0303030303030303030303030303030303030303030303030303030303030303; INST "main_mem_B/gldata_ram2" INIT_03 = 0000000000000000000000000000000000000000000000020202020003020202; INST "main_mem_B/gldata_ram2" INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000; INST "main_mem_B/gldata_ram2" INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000; INST "main_mem_B/gldata_ram3" INIT_00 = 0202020303030303030303030303030303030303030303030303030303034743; INST "main_mem_B/gldata_ram3" INIT_01 = 0303030303030303030303030303030303030303030303030303030303030303; INST "main_mem_B/gldata_ram3" INIT_02 = 0303030303030303030303030303030303030303030303030303030303030303; INST "main_mem_B/gldata_ram3" INIT_03 = 0000000000000000000000000000000000000000000000020202020003020202; INST "main_mem_B/gldata_ram3" INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000; INST "main_mem_B/gldata_ram3" INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000; INST "main_mem_B/gldata_ram3" INIT_1E = 0000000000000000000000000000000000000000000000030200000000000000; INST "main_mem_B/gldata_ram3" INIT_2A = 0000000000000000000000000000000000000000020300000000000000000000; PIN "takt0/DCM_inst.CLKFX" TNM = "clk_sram"; TIMESPEC "TS_takt0" = PERIOD "clk_sram" 13 ns HIGH 50 %; #PIN "sram0.clk_cpu" TNM = "clk_cpu" #TIMESPEC "TS_SRAMSRAM" = FROM "clk_sram" TO "clk_sram" TIG; INST "sram0/datawrite_0_Mem_0" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_1" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_2" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_3" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_4" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_5" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_6" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_7" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_8" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_9" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_10" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_11" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_12" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_13" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_14" TNM = "SRAM0DATAW"; INST "sram0/datawrite_0_Mem_15" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_0" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_1" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_2" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_3" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_4" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_5" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_6" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_7" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_8" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_9" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_10" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_11" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_12" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_13" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_14" TNM = "SRAM0DATAW"; INST "sram0/datawrite_1_Mem_15" TNM = "SRAM0DATAW"; INST "sram0/dmem_out_0" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_1" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_2" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_3" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_4" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_5" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_6" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_7" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_8" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_9" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_10" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_11" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_12" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_13" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_14" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_15" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_16" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_17" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_18" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_19" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_20" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_21" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_22" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_23" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_24" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_25" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_26" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_27" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_28" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_29" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_30" TNM = "SRAM0DMEM"; INST "sram0/dmem_out_31" TNM = "SRAM0DMEM"; #TIMESPEC "TS_EXMPTSRAM0WM" = FROM "SRAM0DATAW" TO "SRAM0DMEM" TIG; #TIMESPEC "TS_EXMPTSRAM0MW" = FROM "SRAM0DMEM" TO "SRAM0DATAW" TIG;