`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:34:42 11/25/2006 
// Design Name: 
// Module Name:    gldata 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mem_sync_VGA ( ena, dia, doa, addra, wea, ssra,
	enb, dob, addrb, clka, clkb);


input[31:0] dia;

output[31:0] doa;

output[31:0] dob;
// reg[31:0] gl_dob;

input[3:0] ena;
input[3:0] wea;

input[3:0] ssra;

input[3:0] enb;
wire[3:0] web;

input[14:0] addrb;
input[14:0] addra;

input clka, clkb;
	


wire[10:0] gl_addrb;
wire[10:0] gl_addrb0;
wire[10:0] gl_addrb1;
wire[10:0] gl_addrb2;
wire[10:0] gl_addrb3;

wire[10:0] gl_addra;


assign gl_addrb = addrb[12:2];
assign gl_addra = addra[12:2];

assign gl_addrb0 = gl_addrb;
assign gl_addrb1 = gl_addrb;
assign gl_addrb2 = gl_addrb;
assign gl_addrb3 = gl_addrb;

reg[3:0] ena_1;
reg[3:0] enb_1;

reg[3:0] wea_1;

wire[3:0] ena0 = {4{ena[0]}};
wire[3:0] wea0 = {4{wea[0]}};

wire[3:0] enb0 = {4{enb[0]}};

wire[3:0] web_1 = 4'b0;


always @(addra, ena0, wea0)
	case (addra[14:13])
	2'd0: begin 
				ena_1 <= 4'b0001 & ena0;
				wea_1 <= 4'b0001 & wea0;
			end
	2'd1: begin 
				ena_1 <= 4'b0010 & ena0;
				wea_1 <= 4'b0010 & wea0;
			end
	2'd2: begin 
				ena_1 <= 4'b0100 & ena0;
				wea_1 <= 4'b0100 & wea0;
			end
	2'd3: begin 
				ena_1 <= 4'b1000 & ena0;
				wea_1 <= 4'b1000 & wea0;
			end
	endcase



always @(addrb, enb0)
	case (addrb[14:13])
	2'd0: begin 
				enb_1 <= 4'b0001 & enb0;
			end
	2'd1: begin 
				enb_1 <= 4'b0010 & enb0;
			end
	2'd2: begin 
				enb_1 <= 4'b0100 & enb0;
			end
	2'd3: begin 
				enb_1 <= 4'b1000 & enb0;
			end
	endcase

// delayed enables
	
reg[3:0] ena_1_1;	
	
always @(posedge clka)
	ena_1_1 <= ena_1;

reg[3:0] enb_1_1;	
	
always @(posedge clkb)
	enb_1_1 <= enb_1;





wire[7:0] gl_dob0;
wire[7:0] gl_dob1;
wire[7:0] gl_dob2;
wire[7:0] gl_dob3;

wire[1:0] gl_dob_aux;

wire[7:0] gl_doa0;
wire[7:0] gl_doa1;
wire[7:0] gl_doa2;
wire[7:0] gl_doa3;

wire[1:0] gl_doa_aux;


wire[7:0] gl_dia0;
wire[7:0] gl_dia1;
wire[7:0] gl_dia2;
wire[7:0] gl_dia3;

assign gl_dia0 = dia[7:0];
assign gl_dia1 = dia[7:0];
assign gl_dia2 = dia[7:0];
assign gl_dia3 = dia[7:0];

wire[7:0] gl_dib;

			
RAMB16_S9_S9 gldata_ram0 (  .DOA ( gl_doa0 ),
									.DOB ( gl_dob0 ),
									.DOPA ( gl_dopa0 ),
									.DOPB ( gl_dopb0 ),
									.ADDRA ( gl_addra ),
									.ADDRB ( gl_addrb0 ),
									.CLKA ( clka ),
									.CLKB ( clkb ),
									.DIA ( gl_dia0 ),
									.DIB ( gl_dib ),
									.DIPA ( gl_dipa ),
									.DIPB ( gl_dipb ),
									.ENA ( ena_1[0] ),
									.ENB ( enb_1[0] ),
									.SSRA ( ssra0 ),
									.SSRB ( gl_ssrb ),
									.WEA ( wea_1[0] ),
									.WEB ( web_1[0] ) );

RAMB16_S9_S9 gldata_ram1 (  .DOA ( gl_doa1 ),
									.DOB ( gl_dob1 ),
									.DOPA ( gl_dopa1 ),
									.DOPB ( gl_dopb1 ),
									.ADDRA ( gl_addra ),
									.ADDRB ( gl_addrb1 ),
									.CLKA ( clka ),
									.CLKB ( clkb ),
									.DIA ( gl_dia1 ),
									.DIB ( gl_dib ),
									.DIPA ( gl_dipa ),
									.DIPB ( gl_dipb ),
									.ENA ( ena_1[1] ),
									.ENB ( enb_1[1] ),
									.SSRA ( ssra1 ),
									.SSRB ( gl_ssrb ),
									.WEA ( wea_1[1] ),
									.WEB ( web_1[1] ) );

RAMB16_S9_S9 gldata_ram2 (  .DOA ( gl_doa2 ),
									.DOB ( gl_dob2 ),
									.DOPA ( gl_dopa2 ),
									.DOPB ( gl_dopb2 ),
									.ADDRA ( gl_addra ),
									.ADDRB ( gl_addrb2 ),
									.CLKA ( clka ),
									.CLKB ( clkb ),
									.DIA ( gl_dia2 ),
									.DIB ( gl_dib ),
									.DIPA ( gl_dipa ),
									.DIPB ( gl_dipb ),
									.ENA ( ena_1[2] ),
									.ENB ( enb_1[2] ),
									.SSRA ( ssra2 ),
									.SSRB ( gl_ssrb ),
									.WEA ( wea_1[2] ),
									.WEB ( web_1[2] ) );

RAMB16_S9_S9 gldata_ram3 (  .DOA ( gl_doa3 ),
									.DOB ( gl_dob3 ),
									.DOPA ( gl_dopa3 ),
									.DOPB ( gl_dopb3 ),
									.ADDRA ( gl_addra ),
									.ADDRB ( gl_addrb3 ),
									.CLKA ( clka ),
									.CLKB ( clkb ),
									.DIA ( gl_dia3 ),
									.DIB ( gl_dib ),
									.DIPA ( gl_dipa ),
									.DIPB ( gl_dipb ),
									.ENA ( ena_1[3] ),
									.ENB ( enb_1[3] ),
									.SSRA ( ssra3 ),
									.SSRB ( gl_ssrb ),
									.WEA ( wea_1[3] ),
									.WEB ( web_1[3] ) );


wire[12:0] gl_addra_aux = addra[14:2];
wire[12:0] gl_addrb_aux = addrb[14:2];

wire[1:0] gl_dia_aux = dia[9:8];

RAMB16_S2_S2 gldata_aux (  .DOA ( gl_doa_aux ),
									.DOB ( gl_dob_aux ),
									.ADDRA ( gl_addra_aux ),
									.ADDRB ( gl_addrb_aux ),
									.CLKA ( clka ),
									.CLKB ( clkb ),
									.DIA ( gl_dia_aux ),
									.DIB ( gl_dib ),
									.ENA ( ena[1] ),
									.ENB ( enb[1] ),
									.SSRA ( ssra3 ),
									.SSRB ( gl_ssrb ),
									.WEA ( wea[1] ),
									.WEB ( 1'b0 ) );




reg[7:0] doa_0;

always @(gl_doa0, gl_doa1, gl_doa2, gl_doa3, ena_1_1)
	case (ena_1_1)
		4'b0001: doa_0 = gl_doa0;
		4'b0010: doa_0 = gl_doa1;
		4'b0100: doa_0 = gl_doa2;
		4'b1000: doa_0 = gl_doa3;
	endcase

reg[7:0] dob_0;

always @(gl_dob0, gl_dob1, gl_dob2, gl_dob3, enb_1_1)
	case (enb_1_1)
		4'b0001: dob_0 = gl_dob0;
		4'b0010: dob_0 = gl_dob1;
		4'b0100: dob_0 = gl_dob2;
		4'b1000: dob_0 = gl_dob3;
	endcase


assign doa = {16'h0, 6'h0, gl_doa_aux, doa_0};
assign dob = {16'h0, 6'h0, gl_dob_aux, dob_0};


endmodule



module mem_sync_CPU( addr, data, dataout, en, wen, clk, rst);


input[31:0] addr;

input[31:0] data;
output[31:0] dataout;

reg[31:0] gl_doa;

input[3:0] en;
input[3:0] wen;


wire[10:0] gl_addra;

assign gl_addra = addr[12:2];

input clk;
input rst;
	
wire[3:0] gl_ssra = 4'b0;

wire[7:0] gl_doa0;
wire[7:0] gl_doa1;
wire[7:0] gl_doa2;
wire[7:0] gl_doa3;

wire[31:0] gl_dia = data;

wire[7:0] gl_dia0;
wire[7:0] gl_dia1;
wire[7:0] gl_dia2;
wire[7:0] gl_dia3;

assign gl_dia0 = gl_dia[7:0];
assign gl_dia1 = gl_dia[15:8];
assign gl_dia2 = gl_dia[23:16];
assign gl_dia3 = gl_dia[31:24];


/*
reg[3:0] en_r;

always @(posedge clk)
	begin
		en_r <= en;
	end
*/
			
RAMB16_S9 gldata_ram0 (  .DO ( gl_doa0 ),
									.DOP ( gl_dopa0 ),
									.ADDR ( gl_addra ),
									.CLK ( clk ),
									.DI ( gl_dia0 ),
									.DIP ( gl_dipa ),
									.EN ( en[0] ),
									.SSR ( gl_ssra[0] ),
									.WE ( wen[0] ) );

RAMB16_S9 gldata_ram1 (  .DO ( gl_doa1 ),
									.DOP ( gl_dopa1 ),
									.ADDR ( gl_addra ),
									.CLK ( clk ),
									.DI ( gl_dia1 ),
									.DIP ( gl_dipa ),
									.EN ( en[1] ),
									.SSR ( gl_ssra[1] ),
									.WE ( wen[1] ));

RAMB16_S9 gldata_ram2 (  .DO ( gl_doa2 ),
									.DOP ( gl_dopa2 ),
									.ADDR ( gl_addra ),
									.CLK ( clk ),
									.DI ( gl_dia2 ),
									.DIP ( gl_dipa ),
									.EN ( en[2] ),
									.SSR ( gl_ssra[2] ),
									.WE ( wen[2] ));

RAMB16_S9 gldata_ram3 (  .DO ( gl_doa3 ),
									.DOP ( gl_dopa3 ),
									.ADDR ( gl_addra ),
									.CLK ( clk ),
									.DI ( gl_dia3 ),
									.DIP ( gl_dipa ),
									.EN ( en[3] ),
									.SSR ( gl_ssra[3] ),
									.WE ( wen[3] ));

`include "C:\\Dokumente und Einstellungen\\Jürgen Böhm\\Eigene Dateien\\lisp\\micasm\\out0.defparam"
`include "C:\\Dokumente und Einstellungen\\Jürgen Böhm\\Eigene Dateien\\lisp\\micasm\\out1.defparam"
`include "C:\\Dokumente und Einstellungen\\Jürgen Böhm\\Eigene Dateien\\lisp\\micasm\\out2.defparam"
`include "C:\\Dokumente und Einstellungen\\Jürgen Böhm\\Eigene Dateien\\lisp\\micasm\\out3.defparam"

//defparam gldata_ram3.INIT_00 = 256'h12341234;



// assign dataout = ((~(|wen)) & (|en_r)) ? gl_doa : 32'bz;

assign dataout = {gl_doa3, gl_doa2, gl_doa1, gl_doa0};

//always @(dataout)
//	$display ("dataout RAM = %h", dataout );


/*
always @(gl_doa3 or gl_doa2 or gl_doa1 or gl_doa0)
	begin
		gl_doa <= {gl_doa3, gl_doa2, gl_doa1, gl_doa0};
	end
*/

endmodule