`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:19:50 11/21/2006 
// Design Name: 
// Module Name:    ledblock 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module ledblock (zf3, zf2, zf1, zf0, sevseg, anods, ce, clk, rst );

input clk;
input rst;
input ce;

input[3:0] zf3, zf2, zf1, zf0;

output[7:0] sevseg;
reg[7:0] sevseg;

output[3:0] anods;
reg[3:0] anods;



reg slowclk;
reg[17:0] divreg;

reg[3:0] aktziff;	
reg[1:0] state, new_state;


always @(aktziff)
begin
case (aktziff)
	4'b0000: begin
					sevseg = 8'b00000011;
				end
	4'b0001: begin
					sevseg = 8'b10011111;
				end
	4'b0010: begin
					sevseg = 8'b00100101;
				end
	4'b0011: begin
					sevseg = 8'b00001101;
				end
	4'b0100: begin
					sevseg = 8'b10011001;
				end
	4'b0101: begin
					sevseg = 8'b01001001;
				end
	4'b0110: begin
					sevseg = 8'b01000001;
				end
	4'b0111: begin
					sevseg = 8'b00011111;
				end
	4'b1000: begin
					sevseg = 8'b00000001;
				end
	4'b1001: begin
					sevseg = 8'b00001001;
				end
	4'b1010: begin
					sevseg = 8'b00010001;
				end
	4'b1011: begin
					sevseg = 8'b11000001;
				end
	4'b1100: begin
					sevseg = 8'b01100011;
				end
	4'b1101: begin
					sevseg = 8'b10000101;
				end
	4'b1110: begin
					sevseg = 8'b01100001;
				end
	4'b1111: begin
					sevseg = 8'b01110001;
				end
endcase
end

always @(posedge clk or posedge rst)
	begin
		if (rst)
			begin
				divreg <= 18'h8ffff;
				slowclk <= 0;
			end
		else
			begin
				if (divreg == 0)
					begin
						slowclk <= ~slowclk;
						divreg <= 18'b011111111111111111;
					end
				else
					begin
						divreg <= divreg - 1;
					end
			end
	end
	
always @(state)
	begin
		case (state)
			2'b00: begin
						new_state = 2'b01;
					 end
			2'b01: begin
						new_state = 2'b10;
					 end
			2'b10: begin
						new_state = 2'b11;
					 end
			2'b11: begin
						new_state = 2'b00;
					 end
			default:	begin
						 new_state = 2'b00;
						end
		endcase
	end



always @(state)
	begin
		case (state)
			2'b00: begin
						anods = 4'b1110;
					 end
			2'b01: begin
						anods = 4'b1101;
					 end
			2'b10: begin
						anods = 4'b1011;
					 end
			2'b11: begin
						anods = 4'b0111;
					 end
			default:	begin
						 anods = 4'b1111;
						end
		endcase
	end

always @(zf0 or zf1 or zf2 or zf3 or state)
	begin
		case (state)
			2'b00: begin
						aktziff = zf0;
					 end
			2'b01: begin
						aktziff = zf1;
					 end
			2'b10: begin
						aktziff = zf2;
					 end
			2'b11: begin
						aktziff = zf3;
					 end
			default:	begin
						 aktziff = 4'b1111;
						end
		endcase
	end
		


always @(posedge slowclk or posedge rst)
	begin
		if (rst)
			begin
				state = 2'b00;
			end
		else
			begin
				state = new_state;
			end
	end

endmodule