module negator ( x, negx);

input[31:0] x;
output[31:0] negx;

reg[31:0] negx;

always @(x)
	negx <= - x;

endmodule


module wait_admin (mem_op, dtack, waitrq, rst, clk);

input mem_op;
input dtack;

output waitrq;
reg waitrq;

input rst;
input clk;

reg monitor_cycles;

always @(posedge clk or posedge rst)
	begin
		if (rst)
			monitor_cycles <= 0;
		else
			begin
				if (mem_op || (monitor_cycles & (~dtack)))
					begin
						monitor_cycles <= 1;
					end 
				else
					begin
						monitor_cycles <= 0;
					end
			end
	end
	

always @(dtack, monitor_cycles)
	begin
		if ((~dtack) && (monitor_cycles))
			begin
				waitrq <= 1;
			end
		else
			begin
				waitrq <= 0;
			end
	end

endmodule