`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:34:42 11/25/2006 
// Design Name: 
// Module Name:    gldata 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mem_sync_VGA ( gl_ena, gl_dia, gl_addra_l, gl_wea, gl_ssra,
	gl_enb, gl_dob, gl_addrb_l, gl_clka, gl_clkb);


input[31:0] gl_dia;

output[31:0] gl_dob;
// reg[31:0] gl_dob;

input[3:0] gl_ena;
input[3:0] gl_wea;

input[3:0] gl_ssra;

input[3:0] gl_enb;
wire[3:0] gl_web;

input[12:0] gl_addrb_l;
input[12:0] gl_addra_l;


wire[10:0] gl_addrb;
wire[10:0] gl_addrb0;
wire[10:0] gl_addrb1;
wire[10:0] gl_addrb2;
wire[10:0] gl_addrb3;

wire[10:0] gl_addra;


assign gl_addrb = gl_addrb_l[12:2];
assign gl_addra = gl_addra_l[12:2];

assign gl_addrb0 = gl_addrb;
assign gl_addrb1 = gl_addrb;
assign gl_addrb2 = gl_addrb;
assign gl_addrb3 = gl_addrb;


input gl_clka, gl_clkb;
	

wire[7:0] gl_dob0;
wire[7:0] gl_dob1;
wire[7:0] gl_dob2;
wire[7:0] gl_dob3;

wire[7:0] gl_dia0;
wire[7:0] gl_dia1;
wire[7:0] gl_dia2;
wire[7:0] gl_dia3;

assign gl_dia0 = gl_dia[7:0];
assign gl_dia1 = gl_dia[15:8];
assign gl_dia2 = gl_dia[23:16];
assign gl_dia3 = gl_dia[31:24];

wire[7:0] gl_dib;

wire[7:0] gl_doa0;
wire[7:0] gl_doa1;
wire[7:0] gl_doa2;
wire[7:0] gl_doa3;


			
RAMB16_S9_S9 gldata_ram0 (  .DOA ( gl_doa0 ),
									.DOB ( gl_dob0 ),
									.DOPA ( gl_dopa0 ),
									.DOPB ( gl_dopb0 ),
									.ADDRA ( gl_addra ),
									.ADDRB ( gl_addrb0 ),
									.CLKA ( gl_clka ),
									.CLKB ( gl_clkb ),
									.DIA ( gl_dia0 ),
									.DIB ( gl_dib ),
									.DIPA ( gl_dipa ),
									.DIPB ( gl_dipb ),
									.ENA ( gl_ena[0] ),
									.ENB ( gl_enb[0] ),
									.SSRA ( gl_ssra[0] ),
									.SSRB ( gl_ssrb ),
									.WEA ( gl_wea[0] ),
									.WEB ( gl_web[0] ) );

RAMB16_S9_S9 gldata_ram1 (  .DOA ( gl_doa1 ),
									.DOB ( gl_dob1 ),
									.DOPA ( gl_dopa1 ),
									.DOPB ( gl_dopb1 ),
									.ADDRA ( gl_addra ),
									.ADDRB ( gl_addrb1 ),
									.CLKA ( gl_clka ),
									.CLKB ( gl_clkb ),
									.DIA ( gl_dia1 ),
									.DIB ( gl_dib ),
									.DIPA ( gl_dipa ),
									.DIPB ( gl_dipb ),
									.ENA ( gl_ena[1] ),
									.ENB ( gl_enb[1] ),
									.SSRA ( gl_ssra[1] ),
									.SSRB ( gl_ssrb ),
									.WEA ( gl_wea[1] ),
									.WEB ( gl_web[1] ) );

RAMB16_S9_S9 gldata_ram2 (  .DOA ( gl_doa2 ),
									.DOB ( gl_dob2 ),
									.DOPA ( gl_dopa2 ),
									.DOPB ( gl_dopb2 ),
									.ADDRA ( gl_addra ),
									.ADDRB ( gl_addrb2 ),
									.CLKA ( gl_clka ),
									.CLKB ( gl_clkb ),
									.DIA ( gl_dia2 ),
									.DIB ( gl_dib ),
									.DIPA ( gl_dipa ),
									.DIPB ( gl_dipb ),
									.ENA ( gl_ena[2] ),
									.ENB ( gl_enb[2] ),
									.SSRA ( gl_ssra[2] ),
									.SSRB ( gl_ssrb ),
									.WEA ( gl_wea[2] ),
									.WEB ( gl_web[2] ) );

RAMB16_S9_S9 gldata_ram3 (  .DOA ( gl_doa3 ),
									.DOB ( gl_dob3 ),
									.DOPA ( gl_dopa3 ),
									.DOPB ( gl_dopb3 ),
									.ADDRA ( gl_addra ),
									.ADDRB ( gl_addrb3 ),
									.CLKA ( gl_clka ),
									.CLKB ( gl_clkb ),
									.DIA ( gl_dia3 ),
									.DIB ( gl_dib ),
									.DIPA ( gl_dipa ),
									.DIPB ( gl_dipb ),
									.ENA ( gl_ena[3] ),
									.ENB ( gl_enb[3] ),
									.SSRA ( gl_ssra[3] ),
									.SSRB ( gl_ssrb ),
									.WEA ( gl_wea[3] ),
									.WEB ( gl_web[3] ) );


assign gl_dob = {gl_dob3, gl_dob2, gl_dob1, gl_dob0};


endmodule



module mem_sync_CPU( addr, data, en, wen, clk, rst);


input[31:0] addr;

inout[31:0] data;

reg[31:0] gl_doa;

input[3:0] en;
input[3:0] wen;


wire[10:0] gl_addra;

assign gl_addra = addr[12:2];

input clk;
input rst;
	
wire[3:0] gl_ssra = 4'b0;

wire[7:0] gl_doa0;
wire[7:0] gl_doa1;
wire[7:0] gl_doa2;
wire[7:0] gl_doa3;

wire[31:0] gl_dia = data;

wire[7:0] gl_dia0;
wire[7:0] gl_dia1;
wire[7:0] gl_dia2;
wire[7:0] gl_dia3;

assign gl_dia0 = gl_dia[7:0];
assign gl_dia1 = gl_dia[15:8];
assign gl_dia2 = gl_dia[23:16];
assign gl_dia3 = gl_dia[31:24];

reg[3:0] en_r;

always @(posedge clk)
	begin
		en_r <= en;
	end
			
RAMB16_S9 gldata_ram0 (  .DO ( gl_doa0 ),
									.DOP ( gl_dopa0 ),
									.ADDR ( gl_addra ),
									.CLK ( clk ),
									.DI ( gl_dia0 ),
									.DIP ( gl_dipa ),
									.EN ( en[0] ),
									.SSR ( gl_ssra[0] ),
									.WE ( wen[0] ) );

RAMB16_S9 gldata_ram1 (  .DO ( gl_doa1 ),
									.DOP ( gl_dopa1 ),
									.ADDR ( gl_addra ),
									.CLK ( clk ),
									.DI ( gl_dia1 ),
									.DIP ( gl_dipa ),
									.EN ( en[1] ),
									.SSR ( gl_ssra[1] ),
									.WE ( wen[1] ));

RAMB16_S9 gldata_ram2 (  .DO ( gl_doa2 ),
									.DOP ( gl_dopa2 ),
									.ADDR ( gl_addra ),
									.CLK ( clk ),
									.DI ( gl_dia2 ),
									.DIP ( gl_dipa ),
									.EN ( en[2] ),
									.SSR ( gl_ssra[2] ),
									.WE ( wen[2] ));

RAMB16_S9 gldata_ram3 (  .DO ( gl_doa3 ),
									.DOP ( gl_dopa3 ),
									.ADDR ( gl_addra ),
									.CLK ( clk ),
									.DI ( gl_dia3 ),
									.DIP ( gl_dipa ),
									.EN ( en[3] ),
									.SSR ( gl_ssra[3] ),
									.WE ( wen[3] ));

`include "C:\\Dokumente und Einstellungen\\Jürgen Böhm\\Eigene Dateien\\lisp\\micasm\\out0.defparam"
`include "C:\\Dokumente und Einstellungen\\Jürgen Böhm\\Eigene Dateien\\lisp\\micasm\\out1.defparam"
`include "C:\\Dokumente und Einstellungen\\Jürgen Böhm\\Eigene Dateien\\lisp\\micasm\\out2.defparam"
`include "C:\\Dokumente und Einstellungen\\Jürgen Böhm\\Eigene Dateien\\lisp\\micasm\\out3.defparam"

//defparam gldata_ram3.INIT_00 = 256'h12341234;



assign data = ((~(|wen)) & (|en_r)) ? gl_doa : 32'bz;

always @(gl_doa3 or gl_doa2 or gl_doa1 or gl_doa0)
	begin
		gl_doa <= {gl_doa3, gl_doa2, gl_doa1, gl_doa0};
	end

endmodule