`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:25:36 11/21/2006 
// Design Name: 
// Module Name:    main 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////





module main(clk, sevseg, anod, ps2d, ps2c, r, g, b, hs, vs, sw, btn, ld, rst);

// input output declarations

input clk;
input rst;


output[7:0] sevseg;
output[3:0] anod;

input ps2d;


input ps2c;


output r, g, b;

output hs, vs;


input[7:0] sw;
input[2:0] btn;

output[7:0] ld;


// declaring registers and assigns

reg[7:0] ld;

reg[15:0] mastercnt;

wire[15:0] mwire;

assign mwire = mastercnt;


wire[2:0] btnl;

wire btnc0, btnc1, btnc2;

reg btnc;

always @(posedge clk)
	btnc = btnc0 | btnc1 | btnc2;

wire btnu0, btnu1, btnu2;


wire clk2;


// the character memory of the vga card

assign gl_clkb = clk2;
assign gl_clka = clk2;

wire vga_en;
assign gl_enb = vga_en;

wire[23:0] vga_addrb;
wire[31:0] vga_din;

wire[7:0] gl_dob;
wire[7:0] gl_dob1;

wire[12:0] gl_addrb;

assign vga_din = {24'b0, gl_dob[7:0]};
assign gl_addrb = vga_addrb[12:0];


reg gl_ena, gl_wea, gl_ssra;
wire[12:0] gl_addra;
wire[7:0] gl_dia;


reg dob_en;

wire[31:0] gl_dia32;
wire[31:0] gl_dob32;

wire[31:0] gl_addra32;
wire[31:0] gl_addrb32;

wire[3:0] gl_ssra32;
wire[3:0] gl_wea32;
wire[3:0] gl_ena32;

wire[3:0] gl_enb32;

gldata gldat ( .gl_ena (gl_ena32), .gl_dia (gl_dia32), .gl_addra_l(gl_addra32[12:0]), .gl_wea(gl_wea32), .gl_ssra(gl_ssra32),
	.gl_enb(gl_enb32), .gl_dob(gl_dob32), .gl_addrb_l(gl_addrb32[12:0]), .gl_clka(gl_clka), .gl_clkb(gl_clkb));


//assign gl_dob = dob_en ? gl_dob1 : 8'bz;
//assign gl_dob = gl_dob1;

wire[31:0] gl_dobX;
assign gl_dob = gl_dobX[7:0];

// the memory-adaptor

wire[1:0] byte_type;
assign byte_type = 2'b11;

wire zero_val;
assign zero_val = 1'b0;

wire[31:0] din_bus;
assign din_bus = {24'b0,gl_dia};

wire[31:0] addr_a;
assign addr_a = {19'b0, gl_addra};

wire[31:0] addr_b;
assign addr_b = {19'b0, gl_addrb};

mem_adaptor_w memadap_write_a (.dinbus(din_bus), .abus(addr_a),
								.enbus(gl_ena), .webus(gl_wea), .ssrbus (gl_ssra),
								.doutmem(gl_dia32), .amem (gl_addra32), 
								.enmem(gl_ena32), .wemem(gl_wea32),.ssrmem(gl_ssra32),
								.type(byte_type));

mem_adaptor_r memadap_read_b (.doutbus(gl_dobX), .abus(addr_b),
								.enbus(gl_enb), .ssrbus (zero_val),
								.dinmem(gl_dob32), .amem (gl_addrb32),
								.enmem(gl_enb32),
								.type(byte_type));




// the LED block

ledblock led_out ( .zf3(mwire[15:12]), .zf2(mwire[11:8]), .zf1(mwire[7:4]), .zf0(mwire[3:0]),
				.sevseg(sevseg), .anods(anod), .ce(1'b1), .clk(clk), .rst(rst) );


// the three buttons
				
debouncer debounce0 ( .btnin(btn[0]), .bstate(btnl[0]), .btndown(btnc0), .btnup(btnu0), .clk(clk), .rst(rst));				
debouncer debounce1 ( .btnin(btn[1]), .bstate(btnl[1]), .btndown(btnc1), .btnup(btnu1), .clk(clk), .rst(rst));				
debouncer debounce2 ( .btnin(btn[2]), .bstate(btnl[2]), .btndown(btnc2), .btnup(btnu2), .clk(clk), .rst(rst));				


//the vga controller

vgacontrol vgacontrol0 ( .auxin({8'b0,sw[7:0]}), .en(vga_en), .addrout(vga_addrb), .datin(vga_din), 
							.r(r), .g(g), .b(b), .hso(hs), .vso(vs), .clk(clk), .clk2(clk2), .rst(rst) ); 




// the PS/2 controller

wire[7:0] dd;

wire[7:0] ps2data;


ps2control ps2control0 ( .ps2c (ps2c), .ps2d (ps2d), .data (ps2data), .rdy(ps2irq), .clk(clk), .rst(rst));



// the ascii-rom to decode keysyms

wire[7:0] ascii_val;

to_ascii_rom ascii_rom0 (.ps2data( ps2data ), .res1(ascii_val));





// the cpu

wire[31:0] addr_cpu;
wire[31:0] data_cpu;

wire readmem_cpu;
wire writemem_cpu;
wire intrq_cpu;

wire[1:0] cpu_dat_type;

wire[3:0] cpu_ena;

wire[31:0] in_mem_cpu;
wire[31:0] out_mem_cpu;
wire[31:0] addr_mem_cpu;
wire[31:0] addr_mem_cpu_Read;
wire[3:0] we_mem_cpu;

wire[3:0] ssra_cpu;
wire[3:0] ssrb_cpu;


gldata gldat1 ( .gl_ena (4'b1), .gl_dia (out_mem_cpu), .gl_addra_l(addr_mem_cpu), .gl_wea(we_mem_cpu), .gl_ssra(ssra_cpu),
	.gl_enb(4'b1), .gl_dob(in_mem_cpu), .gl_addrb_l(addr_mem_cpu_Read), .gl_clka(gl_clka), .gl_clkb(gl_clkb));



assign cpu_en = readmem_cpu | writemem_cpu;

wire[31:0] data_feed;
wire[31:0] data_get;

assign data_feed = writemem_cpu ? data_cpu : 32'bz;
assign data_cpu = ~writemem_cpu ? data_get : 32'bz;


mem_adaptor_w memadap_cpu_Write (.dinbus(data_feed),.abus(addr_cpu), .enbus(cpu_en), 
									.webus(writemem_cpu), .ssrbus(1'b0),
									.doutmem(out_mem_cpu), .amem(addr_mem_cpu),
									.wemem(we_mem_cpu), .ssrmem(ssra_cpu), .type(cpu_dat_type));

mem_adaptor_r memadap_cpu_Read (.doutbus(data_get), .abus(addr_cpu), .enbus(readmem_cpu), 
									.ssrbus(1'b0),
									.dinmem(in_mem_cpu), .amem(addr_mem_cpu_Read),
									.ssrmem(ssrb_cpu), .type(cpu_dat_type));




cpu cpu0 (.addr(addr_cpu),.data(data_cpu),
				.readmem(readmem_cpu),.writemem(writemem_cpu),.type(cpu_dat_type),
				.intrq(intrq_cpu),
				.rst(rst),
				.clk(clk));




//assign data_cpu = writemem_cpu ? 32'bz : dat32_cpu; 

//assign data_cpu = {data24_cpu, gl_dob};
assign intrq_cpu = 1'b0;


always @(posedge clk or posedge rst)
	begin
		if (rst)
			dob_en <= 1;
		else
			dob_en <= 1;
	end











// control of screen by ps2data

reg[12:0] xpos, xpos1;
reg[12:0] ypos, ypos1;
reg[7:0] writechar;

reg[2:0] stat_rd;
reg[1:0] cnt;


reg[12:0] gl_addra_c;
reg[7:0] gl_dia_c;

assign gl_addra = gl_addra_c;
assign gl_dia = gl_dia_c;

wire[12:0] xysum, xysum1;
assign xysum = xpos + ypos;
assign xysum1 = xpos1 + ypos1;


`define linelen 133

always @(posedge clk or posedge rst)
	begin
		if (rst)
			begin

				gl_ena <= 1'b0;
				gl_wea <= 1'b0;
				gl_ssra <= 1'b0;
				gl_addra_c <= 13'b0;
				gl_dia_c <= 8'b0;
				cnt <= 0;


				stat_rd <= 0;
				xpos <= 10;
				ypos <= (2 * `linelen);
				xpos1 <= 10;
				ypos1 <= (2 * `linelen);
				writechar <= 8'h21;
			end
		else
			begin
				case (stat_rd)
				0: begin						
						gl_wea <= 0;
						gl_ssra <= 0;
						gl_ena <= 0;
						stat_rd <= 0;
						if (ps2irq) begin
							if (cnt == 0) begin
								writechar <= ps2data;
								stat_rd <= 3;
								case (ps2data)
									8'h75: 	begin
													xpos1 <= xpos;
													if (ypos >= `linelen)
														ypos1 <= ypos - `linelen;
													else
														ypos1 <= ypos;
													stat_rd <= 3;
												end
									8'h72: 	begin
													xpos1 <= xpos;
													if (ypos < (49 * `linelen))
														ypos1 <= ypos + `linelen;
													else
														ypos1 <= ypos;
													stat_rd <= 3;
												end
									8'h74: 	begin
													ypos1 <= ypos;
													if (xpos < (`linelen - 1))
														xpos1 <= xpos + 1;
													else
														xpos1 <= xpos;
													stat_rd <= 3;
												end
									8'h6b: 	begin
													ypos1 <= ypos;
													if (xpos > 0)
														xpos1 <= xpos - 1;
													else
														xpos1 <= xpos;
													stat_rd <= 3;
												end
									8'hF0: 	begin
													cnt <= 1;
													stat_rd <= 0;
												end
									default: begin
													if (ascii_val != 8'hff)
													begin
														writechar <= ascii_val;
														stat_rd <= 2;
													end
													else
													begin
														stat_rd <= 0;
													end
												end
								endcase
							end else 
							if (cnt == 1) begin
									stat_rd <= 0;
									cnt <= 0;
							end
						end
					end
				2: begin
						gl_addra_c <= xysum;
						gl_dia_c <= writechar;
						gl_wea <= 1;
						gl_ssra <= 1;
						gl_ena <= 1;
						if (xpos < (`linelen - 1))
							xpos <= xpos + 1;
						stat_rd <= 0;
					end
				3: begin
						gl_addra_c <= xysum;
						gl_dia_c <= 8'h20;
						gl_wea <= 1;
						gl_ssra <= 1;
						gl_ena <= 1;
						stat_rd <= 4;
					end
				4: begin
						gl_addra_c <= xysum;
						gl_dia_c <= 8'h20;
						gl_wea <= 0;
						gl_ssra <= 0;
						gl_ena <= 0;
						xpos <= xpos1;
						ypos <= ypos1;
						stat_rd <= 5;
					end
				5: begin
						gl_addra_c <= xysum;
						gl_dia_c <= writechar;
						gl_wea <= 1;
						gl_ssra <= 1;
						gl_ena <= 1;
						stat_rd <= 0;
					end
				endcase
			end
	end




// controls the leds

always @(posedge clk or posedge rst)
	begin
		if (rst)
			ld <= 8'h00;
		else
			ld <= ps2data & (~sw);
	end


// sets mastercnt from ps2data

always @(posedge clk or posedge rst)
	begin
		if (rst)
			begin
				mastercnt <= 800 - 1;
			end
		else
			begin
				if (sw[7]) begin
					if (sw[0])
						mastercnt <= xpos;
					else
						mastercnt <= ypos;
				end else begin
					if (sw[6])
						if (sw[5])
							mastercnt <= data_cpu[15:0];
						else
							mastercnt <= data_cpu[31:16];
					else
						mastercnt <= addr_cpu[15:0];
				end		
			end
	end

endmodule




module ps2control ( ps2c, ps2d, data, rdy, clk, rst);

input ps2c;
input ps2d;

output data;
output rdy;

reg rdy;

input clk, rst;

reg[10:0] psreg;

reg[7:0] data;

reg ps10;

always @(posedge clk or posedge rst)
	begin
		if (rst)
			begin
				ps10 <= 1;
			end
		else
			begin
				if (~psreg[0])
					begin
						ps10 <= 1;
					end
				else
					begin
						ps10 <= 0;
					end
				end
	end

reg ps10_1;

always @(posedge clk)
	ps10_1 <= ps10;

assign rdy1 = ps10 & (~ps10_1);
		
always @(posedge clk or posedge rst)
	begin
		if (rst)
			begin
				data <= 0;
				rdy <= 0;
			end
		else
			begin
				if (rdy1)
					data <= psreg[8:1];
				if (rdy)
					rdy <= 0;
				else
					rdy <= rdy1;
			end
	end

always @(negedge ps2c or posedge rst)
	begin
		if (rst)
			begin
				psreg <= 11'b11111111111;
			end
		else
			begin
				if (~psreg[0])
					begin
						psreg <= {ps2d, 10'b1111111111};
					end
				else
					begin
						psreg <= {ps2d, psreg[10:1]};
					end
			end
	end	

endmodule


module to_ascii_rom (ps2data, res1);

input[7:0] ps2data;
output[7:0] res1;

reg[7:0] res1;
reg[7:0] res;

always @(res)
	begin
		case (res)
			8'd32: res1 <= res;
			8'hff: res1 <= res;
			default: res1 <= res + 8'd32;
		endcase
	end


always @(ps2data)
begin
case (ps2data)
//a b c d e
8'h1C:res=8'd65;
8'h32:res=8'd66;
8'h21:res=8'd67;
8'h23:res=8'd68;
8'h24:res=8'd69;
//f g h i j
8'h2B:res=8'd70;
8'h34:res=8'd71;
8'h33:res=8'd72;
8'h43:res=8'd73;
8'h3B:res=8'd74;
//k l m n o
8'h42:res=8'd75;
8'h4B:res=8'd76;
8'h3A:res=8'd77;
8'h31:res=8'd78;
8'h44:res=8'd79;
//p q r s t
8'h4D:res=8'd80;
8'h15:res=8'd81;
8'h2D:res=8'd82;
8'h1B:res=8'd83;
8'h2C:res=8'd84;
//u v w x y
8'h3C:res=8'd85;
8'h2A:res=8'd86;
8'h1D:res=8'd87;
8'h22:res=8'd88;
8'h35:res=8'd90;
//z
8'h1A:res=8'd89;
//space
8'h29:res=8'd32;
default: res=8'hFF;
endcase
end
endmodule