////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 8.1.03i
//  \   \         Application : ISE
//  /   /         Filename : cpu_tb.tfw
// /___/   /\     Timestamp : Mon Nov 12 01:08:47 2007
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: cpu_tb
//Device: Xilinx
//
`timescale 1ns/1ps

module cpu_tb;
    wire [31:0] addr;
    reg [31:0] data$inout$reg = 32'b00000000000000000000000000000000;
    // wire [31:0] data = data$inout$reg;
		wire [31:0] data;
    wire readmem;
    wire writemem;
    reg intrq = 1'b0;
    wire [1:0] type;
    reg rst = 1'b1;
    reg clk = 1'b0;

    parameter PERIOD = 20;
    // parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
//            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
//            #(PERIOD*DUTY_CYCLE);
              #10 clk = 1'b1;
              #10;
       end
    end
		
		initial
		begin
			$monitor ( "addr = %h data = %h readmem = %h writemem = %h datamem_i = %h datamem = %h wmem = %h clk= %h",
								addr, data, readmem, writemem, datamem_i, datamem, wmem, clk ); 
		end

    cpu UUT (
        .addr(addr),
        .data(data),
        .readmem(readmem),
        .writemem(writemem),
        .intrq(intrq),
        .type(type),
        .rst(rst),
        .clk(clk));
				
		
		wire [3:0] ssrmem;
		wire [3:0] wemem;
		wire [3:0] enmem;
		wire [3:0] enmem1;
		
		wire [31:0] datamem_o;
		wire [31:0] datamem_i;
		
		wire [31:0] data_b_w;
		wire [31:0] data_b_r;
		
		wire [31:0] amem_w;
		wire [31:0] amem_r;

		wire[31:0] addrmem;
		wire[31:0] datamem;
		wire[3:0] wmem;
		
		wire rack;
		
		mem_adaptor_w maw0 (.dinbus(data_b_w),.abus(addr), .enbus(1'b1), .webus(writemem),
														.ssrbus(1'b1),
												.doutmem(datamem_o), .amem(amem_w), .enmem(enmem1),
													.wemem(wmem), .ssrmem(ssrmem), .type(2'b10));
		
		mem_adaptor_r mar0 (.doutbus(data_b_r),.abus(addr), .enbus(readmem),
														.ssrbus(1'b1), .read_ack (rack),
												.dinmem(datamem_i), .amem(amem_r), .enmem(enmem),
													.ssrmem(ssrmem), .type(2'b00), .clk(clk));
	
		
		assign addrmem = writemem ? amem_w : amem_r;

		assign datamem = writemem ? datamem_o : 32'bz;
		
		assign datamem_i = ((~writemem) & rack) ? datamem : 32'bz;
		
		assign data = rack ? data_b_r : 32'bz;
		
		assign data_b_w = writemem ? data : 32'bz;
		
				
		mem_sync main_mem0 (.addr(addrmem), .data(datamem), .en(enmem), .write(wmem), .clk(clk));

    integer TX_FILE = 0;
    integer TX_ERROR = 0;
    
    initial begin  // Open the results file...
        TX_FILE = $fopen("results.txt");
        #1020 // Final time:  1020 ns
        if (TX_ERROR == 0) begin
            $display("No errors or warnings.");
            $fdisplay(TX_FILE, "No errors or warnings.");
        end else begin
            $display("%d errors found in simulation.", TX_ERROR);
            $fdisplay(TX_FILE, "%d errors found in simulation.", TX_ERROR);
        end
        $fclose(TX_FILE);
        $stop;
    end

    initial begin
        // -------------  Current Time:  29ns
        #29;
        rst = 1'b0;
        data$inout$reg = 32'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ;
        // -------------------------------------
    end

    task CHECK_addr;
        input [31:0] NEXT_addr;

        #0 begin
            if (NEXT_addr !== addr) begin
                $display("Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr);
                $fdisplay(TX_FILE, "Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask
    task CHECK_readmem;
        input NEXT_readmem;

        #0 begin
            if (NEXT_readmem !== readmem) begin
                $display("Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem);
                $fdisplay(TX_FILE, "Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask
    task CHECK_writemem;
        input NEXT_writemem;

        #0 begin
            if (NEXT_writemem !== writemem) begin
                $display("Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem);
                $fdisplay(TX_FILE, "Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask
    task CHECK_type;
        input [1:0] NEXT_type;

        #0 begin
            if (NEXT_type !== type) begin
                $display("Error at time=%dns type=%b, expected=%b", $time, type, NEXT_type);
                $fdisplay(TX_FILE, "Error at time=%dns type=%b, expected=%b", $time, type, NEXT_type);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask

endmodule