The Details

For those who want to know more: The folder with the actual current ISE-project and the other folders where microprogram, compiler and auxiliary files are situated can be found here:

Please note that all files are Copyright by Jürgen Böhm, 2006, 2007, 2008 unless marked to the contrary, even if no disclaimer of copyright is included in the files themselves.

• The ISE-project at www.aviduratas.de/fpga/Proto200
• Microassembler, microcode and Icarus simulation evironment at www.aviduratas.de/lisp/lisp/micasm/
• Compiler and Emulator at www.aviduratas.de/lisp/lisp/mevalxp/
• VGA-Screen-Emulator implemented with Icarus/Linux, VPI and Qt at www.aviduratas.de/fpga/simuqt
• Full instruction level simulator of the complete LispmFPGA System (finished up to some possible enhancements that are not strictly necessary). www.aviduratas.de/fpga/simemu

If you really want to get the above code run at your place and need more informations (which are of course necessary as I did not write documentation yet) please write me a mail at juergen.boehm@aviduratas.de

An excerpt from the Verilog for the E-Processor (main microcode control loop):

assign waitrq1 = waitrq & cycle_start;


always @(mic_next, datamem, dispatch, waitrq1, micr_pc, micr_pc_new, 
rst, ir, tos, to_page_zero, irq_cycle_start)
	begin
		if (rst) begin
			micr_pc_new <= 62* 8;
			tosout <= 0;
		end else begin
			if (~waitrq1)
				begin
					debugout <= {16'b0,ir[31:16]};
					if (ir[23:16] == 8'd60)
						tosout <= tos;
					if (to_page_zero)
						begin
							micr_pc_new <= {6'b0, mic_next};
						end
					else if (irq_cycle_start)
						begin
							$display ( "irq cycle start.");
							micr_pc_new <= {1'b0, 6'd14, 3'b0};
						end
					else if (dispatch)
						begin
							micr_pc_new <= {1'b0,datamem[21:16],mic_next[2:0]};
						end
					else
						begin
							micr_pc_new <= {micr_pc[9:4],mic_next};
						end
				end
			else
				begin
					micr_pc_new <= micr_pc;
				end
		end
	end


always @(posedge clk or posedge rst)
	begin
		if (rst)
			begin
				micr_pc <= 62* 8;
			end
		else
			begin
				micr_pc <= micr_pc_new;
			end
		
	end



`define mic_inst_wait {5'd31, 5'd7, 5'd31, 3'd7, 3'd4, 3'd4, 1'd0, 1'd0, 2'd0, 4'd0}
`define mic_inst_wait_h {18'd0, 3'd1, 1'd0, 2'd0, 1'd0, 1'd0, 6'd63}


always @(waitrq1, rst, mic_inst_raw, mic_inst_h_raw)
	begin
		if (~waitrq1 & ~rst)
			begin
				mic_inst <= mic_inst_raw;
				mic_inst_h <= mic_inst_h_raw;
			end
		else
			begin
				mic_inst <= `mic_inst_wait;
				mic_inst_h <= `mic_inst_wait_h;
			end
	end
	


micro_store mcs0 ( .address({micr_pc_new[9:0]}), .data(mic_inst_raw), .read_en(1'b1), .ce(1'b1), .clk(clk)); 
micro_store_1 mcs1 ( .address({micr_pc_new[9:0]}), .data(mic_inst_h_raw), .read_en(1'b1), .ce(1'b1), .clk(clk));

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      Zuletzt geändert - 17 02 2008