LispmFPGA

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The Details

For those who want to know more: The folder with the actual current ISE-project and the other folders where microprogram, compiler and auxiliary files are situated can be found here:

Please note that all files are Copyright by Jürgen Böhm, 2006 - 2011 unless marked to the contrary, even if no disclaimer of copyright is included in the files themselves.

The code itself has gone through several major stages of revision. I codenamed them cedar, quibus and tetrad, which is the newest. (tetrad means copybook in russian, no connection to this meaning intended). For each of these revision I prepared a packaging of all the files belonging to the project, not only the Verilog-Files, but also the Lisp-Code and the C++--Sources of the VGA-Screen-Emulator (simuqt) and the full instruction level simulator (simemu).

In the packaging I followed a scheme often found on opencores:

  • tetrad-001/bin
  • tetrad-001/tst
  • tetrad-001/src/simuqt/templates
  • tetrad-001/src/simuqt/bin
  • tetrad-001/src/simuqt/src
  • tetrad-001/src/simuqt
  • tetrad-001/src/simemu/templates
  • tetrad-001/src/simemu/bin
  • tetrad-001/src/simemu/src
  • tetrad-001/src/simemu
  • tetrad-001/src
  • tetrad-001/lisp/mevalxp/concepts
  • tetrad-001/lisp/mevalxp/system
  • tetrad-001/lisp/mevalxp/tests
  • tetrad-001/lisp/mevalxp
  • tetrad-001/lisp/micasm
  • tetrad-001/lisp
  • tetrad-001/doc
  • tetrad-001/rtl
  • tetrad-001
  • Here ./rtl contains the Verilog sources intended to be compiled into hardware, ./tst contains Verilog testbed sources, testscripts and related files. ./lisp of course contains all lisp files belonging to the project, with ./mevalxp containing the compiler and ./system and ./tests containing files to be compiled and run on the lispm-fpga-hardware or on the simulators, for testing purposes. Especially the ./system folder contains the necessary files for the mini-'OS' on the hardware which provides a garbage collector and a full-screen text-editor (which is intended to be integrated with a lisp-interpreter later).

    The ./src directories contain the C++ code of the programs simuqt (which is a simulator meant to be used in connection with the testbed code in ./tst) and simemu (which is a freestanding instruction level simulator). The latter requires also kdelibs at the moment. The author recommends first getting the 'OS'-software of lispm-fpga to run on simemu. A good place to start is to look in comp-test.lisp, especially the 'doit..'- and 'test..'-functions and roll the analysis back from them.

    The files


    The newest stage of the project, prepackaged: tetrad-001.tgz
    Overview of all project files from all stages of the project.

    If you really want to get the above code run at your place and need more informations (which are of course necessary as I did not write documentation yet) please write me a mail at juergen.boehm@aviduratas.de

    A Verilog excerpt

    An excerpt from the Verilog for the E-Processor (main microcode control loop):

    assign waitrq1 = waitrq & cycle_start;
    
    
    always @(mic_next, datamem, dispatch, waitrq1, micr_pc, micr_pc_new, 
    rst, ir, tos, to_page_zero, irq_cycle_start)
    	begin
    		if (rst) begin
    			micr_pc_new <= 62* 8;
    			tosout <= 0;
    		end else begin
    			if (~waitrq1)
    				begin
    					debugout <= {16'b0,ir[31:16]};
    					if (ir[23:16] == 8'd60)
    						tosout <= tos;
    					if (to_page_zero)
    						begin
    							micr_pc_new <= {6'b0, mic_next};
    						end
    					else if (irq_cycle_start)
    						begin
    							$display ( "irq cycle start.");
    							micr_pc_new <= {1'b0, 6'd14, 3'b0};
    						end
    					else if (dispatch)
    						begin
    							micr_pc_new <= {1'b0,datamem[21:16],mic_next[2:0]};
    						end
    					else
    						begin
    							micr_pc_new <= {micr_pc[9:4],mic_next};
    						end
    				end
    			else
    				begin
    					micr_pc_new <= micr_pc;
    				end
    		end
    	end
    
    
    always @(posedge clk or posedge rst)
    	begin
    		if (rst)
    			begin
    				micr_pc <= 62* 8;
    			end
    		else
    			begin
    				micr_pc <= micr_pc_new;
    			end
    		
    	end
    
    
    
    `define mic_inst_wait {5'd31, 5'd7, 5'd31, 3'd7, 3'd4, 3'd4, 1'd0, 1'd0, 2'd0, 4'd0}
    `define mic_inst_wait_h {18'd0, 3'd1, 1'd0, 2'd0, 1'd0, 1'd0, 6'd63}
    
    
    always @(waitrq1, rst, mic_inst_raw, mic_inst_h_raw)
    	begin
    		if (~waitrq1 & ~rst)
    			begin
    				mic_inst <= mic_inst_raw;
    				mic_inst_h <= mic_inst_h_raw;
    			end
    		else
    			begin
    				mic_inst <= `mic_inst_wait;
    				mic_inst_h <= `mic_inst_wait_h;
    			end
    	end
    	
    
    
    micro_store mcs0 ( .address({micr_pc_new[9:0]}), .data(mic_inst_raw), .read_en(1'b1), .ce(1'b1), .clk(clk)); 
    micro_store_1 mcs1 ( .address({micr_pc_new[9:0]}), .data(mic_inst_h_raw), .read_en(1'b1), .ce(1'b1), .clk(clk));
    

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